A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

被引：94

作者：

Kim, S ^{[1
]}

Lee, K ^{[1
]}

Moon, Y ^{[1
]}

Jeong, DK ^{[1
]}

Choi, YH ^{[1
]}

Lim, HK ^{[1
]}

机构：

[1] SAMSUNG ELECT CO,YONGIN,KYUNGKI DO,SOUTH KOREA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1997年 / 32卷 / 05期

关键词：

skew-tolerant; high speed bus; oversampling; phase locked loop; jitter; CMOS; phase frequency detector; voltage controlled oscillator;

D O I：

10.1109/4.568836

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes an I/O scheme for use in a highspeed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method, The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise, Measured results show peak-to-peak jitter of 150 ps and rms jitter of 15.7 ps on the clock line, Two experimental chips with 4-pin interface have been fabricated with a 0.6-mu m CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.

引用

页码：691 / 700

页数：10

共 9 条

[1] A NOVEL CMOS DIGITAL CLOCK AND DATA DECODER [J].