CMOS downsizing toward sub-10 nm

被引：35

作者：

Iwai, H ^{[1
]}

机构：

[1] Tokyo Inst Technol, Frontier Collaborat Res Ctr, Yokohama, Kanagawa 2268502, Japan

来源：

SOLID-STATE ELECTRONICS | 2004年 / 48卷 / 04期

关键词：

silicon; transistor; MOSFETs; CMOS; scaling; downsizing;

D O I：

10.1016/j.sse.2003.09.034

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 6 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into the market or not. In this paper, limitation and its possible causes for the downscaling of CMOS towards sub-10 nm are discussed with consideration of past CMOS predictions for the limitation. (C) 2003 Elsevier Ltd. All rights reserved.

引用

页码：497 / 503

页数：7