Improvement in linewidth roughness by postprocessing

被引:45
作者
Chandhok, Manish [1 ]
Frasure, Kent [1 ]
Putna, E. Steve [1 ]
Younkin, Todd R. [1 ]
Rachmady, Willy [1 ]
Shah, Uday [1 ]
Yueh, Wang [1 ]
机构
[1] Intel Corp, Hillsboro, OR 97124 USA
来源
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B | 2008年 / 26卷 / 06期
关键词
nanolithography; photoresists;
D O I
10.1116/1.3013860
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In order to meet the linewidth roughness (LWR) requirements for the 16 nm node, postprocessing methods need to be investigated to reduce the LWR after the lithography step. We present the results of five different techniques applied to a single extreme ultraviolet photoresist. The results show that rinse has the most promise in achieving the nearly two time LWR improvement needed. However, other techniques such as etch/trim, hardbake, vapor smoothing, and ozonation give at least 10%-20% LWR reduction and could be further optimized. Some of the physical based techniques which melt the photoresist reduce the midspatial frequency (50-10 nm period) roughness, whereas chemical based techniques reduce the low order spatial frequencies (similar to 500-50 nm period). Hence, a combination of techniques may be the ultimate solution.
引用
收藏
页码:2265 / 2270
页数:6
相关论文
共 13 条
[1]  
CHANDHOK M, 2007, P SPIE, V6519
[2]   Molecular glass resists as high-resolution patterning materials [J].
De Silva, Anuja ;
Felix, Nelson M. ;
Ober, Christopher K. .
ADVANCED MATERIALS, 2008, 20 (17) :3355-3361
[3]   Rinse additives for line edge roughness control in 193 nm lithography [J].
Goldfarb, DL ;
Burns, SD ;
Burns, RL ;
Brodsky, CJ ;
Lawson, MC ;
Angelopoulos, M .
ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XXI, PTS 1 AND 2, 2004, 5376 :343-351
[4]  
Linton T, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P303, DOI 10.1109/IEDM.2002.1175839
[5]   Line edge roughness reduction by plasma curing photoresists [J].
Mahorowala, AP ;
Chen, KJ ;
Sooriyakumaran, R ;
Clancy, A ;
Murthy, D ;
Rasgon, S .
ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XXII, PT 1 AND 2, 2005, 5753 :380-389
[6]   Experimental and model-based study of the robustness of line-edge roughness metric extraction in the presence of noise [J].
Naulleau, Patrick P. ;
Cain, Jason P. .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2007, 25 (05) :1647-1657
[7]   Effect of hard bake process on LER [J].
Padmanaban, M ;
Rentkiewicz, D ;
Lee, SH ;
Hong, CS ;
Lee, D ;
Rahman, D ;
Sakamuri, R ;
Darnmel, RR .
ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XXII, PT 1 AND 2, 2005, 5753 :862-869
[8]   Line-edge roughness reduction and CD slimming using hardbake processing [J].
Peters, R ;
Lucas, K ;
Cobb, J ;
Parker, C ;
Patterson, K ;
McCauley, R ;
Ercken, M ;
Van Roey, F ;
Vandenbroeck, N ;
Pollentier, I .
METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XVII, PTS 1 AND 2, 2003, 5038 :1131-1142
[9]   Effects of processing parameters on line width roughness [J].
Rice, BJ ;
Cao, H ;
Chandhok, M ;
Meagley, R .
ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2, 2003, 5039 :384-392
[10]   Exposing extreme ultraviolet lithography at Intel [J].
Roberts, Jeanette ;
Bacuita, Terence ;
Bristol, Robert L. ;
Cao, Heidi ;
Chandhok, Manish ;
Lee, Sang H. ;
Leeson, Michael ;
Liang, Ted ;
Panning, Eric ;
Rice, Bryan J. ;
Shah, Uday ;
Shell, Melissa ;
Yueh, Wang ;
Zhang, Guojing .
MICROELECTRONIC ENGINEERING, 2006, 83 (4-9) :672-675