A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops

被引：56

作者：

Chang, BS

Park, JB

Kim, WC

机构：

[1] Dept. of Electronics Engineering, Seoul National University, Kwanak-gu

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1996年 / 31卷 / 05期

关键词：

D O I：

10.1109/4.509860

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 1.2 GHz dual-modulus prescaler IC fabricated with 0.8 mu m CMOS technology is presented in this paper. The dual-modulus prescaler includes a synchronous counter (divide-by-4/5) and an asynchronous counter (divide-by-32). A new dynamic D-flip-flop (DFF) is developed for high-speed synchronous counter. The maximum operating frequency of 1.22 GHz with power consumption of 25.5 mW has been measured at 5 V supply voltage.

引用

页码：749 / 752

页数：4

共 7 条

[1]

CONG HI, 1988, ISSCC FEB, P138

[2] CMOS HIGH-SPEED DUAL-MODULUS FREQUENCY-DIVIDER FOR RF FREQUENCY-SYNTHESIS [J].