Monte Carlo simulation of low voltage hot carrier effects in non volatile memory cells

Recent experiments on MOSFETs and non-volatile memory cells [1] indicated a non-trivial bias and temperature dependence of substrate (I-B) and gate (I-G) currents whenever the drain voltage (V-DS) becomes comparable to the critical values corresponding to the band gap, and the Si-SiO2 barrier energies. In this paper, the experiments of [1] are analyzed by means of detailed Monte Carlo simulations. The role held by electron-electron scattering (EES), impact ionization feedback (IIF), band gap variations with temperature (Delta E(G)) and tunneling through the barrier in explaining the experimental results is pointed out.