Estimation of ground bounce effects on CMOS circuits

被引:38
作者
Kabbani, A [1 ]
Al-Khalili, AJ [1 ]
机构
[1] Concordia Univ, Dept Elect & Comp Engn, Montreal, PQ H3G 1M8, Canada
来源
IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES | 1999年 / 22卷 / 02期
关键词
CMOS; ground bounce; simultaneous switching noise; VLSI;
D O I
10.1109/6144.774752
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Ground bounce estimation is important to determine the impact of simultaneous switching of input/output (I/O) drivers and clock drivers on the performance of application-specific integrated circuits (ASIC's), In this paper, we develop models to estimate the peak and damped resonance noise of the ground and power bounce. These models are developed for both long and short channel devices. Comparison with H-simulation program with integrated circuit emphasis (HSPICE) simulation indicates a good match. These models are simple and suitable for hand calculation.
引用
收藏
页码:316 / 325
页数:10
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