Low temperature growth and reliability of ferroelectric memory cell integrated on Si with conducting barrier stack

被引:7
作者
Dhote, AM
Madhukar, S
Young, D
Venkatesan, T
Ramesh, R
Cotell, CM
Benedetto, JM
机构
[1] USN,RES LAB,SURFACE MODIFICAT BRANCH,WASHINGTON,DC 20375
[2] USA,RES LABS,ADELPHI,MD 20783
关键词
D O I
10.1557/JMR.1997.0218
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Polycrystalline LSCO/PNZT/LSCO ferroelectric capacitor heterostructures were grown by pulsed laser deposition using a composite conducting barrier layer of Pt/TiN on poly Si/Si substrate, The growth of the ferroelectric heterostructure is accomplished at a temperature in the range of 500-600 degrees C, This integration results in a 3-dimensional stacked capacitor-transistor geometry which is important for high density nonvolatile memory (HDNVM) applications, Transmission electron microscopy shows smooth substrate-film and film-film interfaces without any perceptible interdiffusion, The ferroelectric properties and reliability of these integrated capacitors were studied extensively at room temperature and 100 degrees C for different growth temperatures. The capacitors exhibit excellent reliability, both at room temperature and at elevated temperatures, making them very desirable for HDNVM applications.
引用
收藏
页码:1589 / 1594
页数:6
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