Three-dimensional 35 nF/mm2 MIM capacitors integrated in BiCMOS technology

被引：24

作者：

Bajolet, A ^{[1
]}

Giraudin, JC ^{[1
]}

Rossato, C ^{[1
]}

Pinzelli, L ^{[1
]}

Bruyère, S ^{[1
]}

Crémer, S ^{[1
]}

Jagueneau, T ^{[1
]}

Delpech, P ^{[1
]}

Montès, L ^{[1
]}

Ghibaudo, G ^{[1
]}

机构：

[1] ST Microelect, F-38926 Crolles, France

来源：

PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2005年

关键词：

D O I：

10.1109/ESSDER.2005.1546600

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Decoupling applications require high capacitance values. To optimize the chip performances, it appears particularly interesting to integrate them directly in interconnect levels, especially in BiCMOS technology. In order to reach this goal and minimize the area occupied by such devices, three-dimensional MIM capacitors have been introduced with different dielectrics: Ta(2)O(5) deposited by MOCVD and Al(2)O(3) by ALD. Thus, high capacitance density of 35nF/mm(2) has been reached. Through comparison between planar and three dimensional (3D) MIM capacitor characterization, it has been demonstrated that 3D MIM capacitor, named High Density Trench Capacitor (HiDTC), architecture is a very promising candidate to integrate such high capacitance values.

引用

页码：121 / 124

页数：4

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