High-voltage-tolerant I/O buffers with low-voltage CMOS process

被引:60
作者
Singh, GP [1 ]
Salem, RB [1 ]
机构
[1] Sun Microsyst Inc, Palo Alto, CA 94303 USA
关键词
bus overshoot; bus undershoot; cache; gate-oxide stress; input-output (I/O) buffer; microprocessor; SRAM;
D O I
10.1109/4.799855
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents high-voltage-tolerant I/O buffer designs for a 1.9-V external cache interface and a 3.3-V system interface using 1.9-V MOS transistors in a 0.21-mu m process with 40-Angstrom gate-oxide thickness. Various circuit techniques are used for 1.9- and 3.3-V I/O buffers to ensure that the voltage across the gate oxide of every MOS element is below specified limits of 2.2 V for transient (short duty cycle) and 1.9 V for steady state. Only one PMOS pullup driver transistor between the bond pad and the power supply, and one NMOS pulldown driver transistor between the bond pad and ground, are used for the 1.9-V I/O buffer design, while cascoded MOS transistors between the bond pad and power supply or ground terminals are used for the 3.3-V I/O buffer design. The primary design goal is to ensure the reliability of MOS elements by avoiding excessive gate-oxide stress due to high electric fields. However, due to differences in requirements for speed, power-supply voltage, and tristate leakage current, completely different circuit techniques have been used for the two designs. Both of the designs hare been successfully implemented in a 400-MHz UltraSPARC microprocessor.
引用
收藏
页码:1512 / 1525
页数:14
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