Parallel implementation of video encoder on quad DSP system

被引:12
作者
Lehtoranta, O
Hämäläinen, T
Lappalainen, V
Mustonen, J
机构
[1] Tampere Univ Technol, Inst Digital & Comp Syst, Tampere 33720, Finland
[2] Nokia Res Ctr, Tampere 33721, Finland
[3] Elektrobit Ltd, Oulu 90570, Finland
关键词
h.263; video coding; parallel architectures; DSP; TMS320C6201;
D O I
10.1016/S0141-9331(01)00141-7
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Implementation of H.263/MPEG4 video encoder is presented for a demanding vehicle remote control system. Required features are CIF-sized images, over 25 fps frame rate and flexibility to realize different coding modes and algorithms. A fully DSP-based implementation is chosen, in which the number of processors is scaleable. Out of parallel mapping approaches, a column-wise data parallel method in a master-slave configuration is chosen. A detailed performance analysis shows that the requirements are clearly exceeded with two TMS320C6201 processors while obtaining over 90% parallelization efficiency. Estimations are also -given for a larger number of DSPs and image sizes. (C) 2002 Elsevier Science B.V. All rights reserved.
引用
收藏
页码:1 / 15
页数:15
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