Giga bit per second per pin differential CMOS circuits for pseudo ECL signaling

被引：2

作者：

Djahanshahi, H ^{[1
]}

Hansen, F ^{[1
]}

Salama, CAT ^{[1
]}

机构：

[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada

来源：

PROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 1999年

关键词：

D O I：

10.1109/CICC.1999.777353

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents high-speed differential CMOS circuits for giga bit per second serial data transmission, The circuits include input and output (I/O) interfaces and a flipflop for retiming. Signal levels are compatible with industry standards for low-voltage positive ECL, with the possibility of ac-coupling to standard ECL systems. A differential open-drain circuit with pulsed bias and active pull-ups offers significantly improved speed performance for a transmitter and creates wide open eye patterns. The circuits were implemented in a 0.35 mu m CMOS process and tested at 622Mb/s and 1.24Gb/s. The asynchronous performances of the transmitter and the receiver were tested at rates up to 2.5Gb/s.

引用

页码：601 / 604

页数：4