Nanoscale CMOS spacer FinFET for the terabit era

被引:135
作者
Choi, YK [1 ]
King, TJ [1 ]
Hu, CM [1 ]
机构
[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
关键词
chemical mechanical polishing (CMP); critical dimension (CD); double-gate; finFET; gate planarization; nanoscale CMOS; silicon-on-insulator (SOI); spacer etch; spacer lithography; thin-body; uniformity;
D O I
10.1109/55.974801
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A spacer lithography process technology, which uses a sacrificial layer and spacer layer formed by chemical vapor deposition (CVD), has been developed. It has been applied to make a sub-40-nm Si-fin structure for a double-gate FinFET with conventional dry etching for the first time. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this spacer lithography technology yields better critical dimension uniformity than conventional optical or e-beam lithography and defines smaller features beyond the limit of current lithography technology. It also provides a doubling of feature density for a given lithography pitch, which increases current by a factor of two. To demonstrate this spacer lithography technology, Si-fin structures have been patterned for planar double-gate CMOS FinFET devices.
引用
收藏
页码:25 / 27
页数:3
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