共 4 条
Simulation of the variability in microelectronic capacitors having polycrystalline dielectrics
被引:3
作者:
Cousins, JL
[1
]
Kotecki, DE
[1
]
机构:
[1] Univ Maine, Dept Elect & Comp Engn, Orono, ME 04469 USA
关键词:
dielectric films;
DRAM chips;
random access memories (RAM);
semiconductor device modeling;
simulation;
D O I:
10.1109/55.998872
中图分类号:
TM [电工技术];
TN [电子技术、通信技术];
学科分类号:
0808 ;
0809 ;
摘要:
The scaling down of on-chip microelectronic capacitors presents a considerable challenge for future microelectronic devices. High-permittivity polycrystalline dielectrics such as Ta2O5, SrTiO3 (STO), or (Ba, Sr)TiO3 (BSTO), have been considered as potential replacement for conventional amorphous SiO2 and SiNx. The polycrystalline microstructure of these materials may lead to capacitor-to-capacitor variations in charge storage capacity and charge retention. In this letter, a Monte Carlo simulation is used to assess these variations. Results show that as the average crystalline grain size becomes greater than 1% of the capacitor size, variations of +/-10% in capacitance and between 3-150% in leakage should be expected.
引用
收藏
页码:267 / 269
页数:3
相关论文