FPGA based hardware architecture for HIT/DLR hand

被引:28
作者
Wei, R [1 ]
Gao, XH [1 ]
Jin, MH [1 ]
Liu, YW [1 ]
Liu, H [1 ]
Seitz, N [1 ]
Gruber, R [1 ]
Hirzinger, G [1 ]
机构
[1] HIT, Robarts Res Inst, Harbin 150001, Peoples R China
来源
2005 IEEE/RSJ INTERNATIONAL CONFERENCE ON INTELLIGENT ROBOTS AND SYSTEMS, VOLS 1-4 | 2005年
关键词
HIT/DLR Hand; FPGA; DSP; PPSeCo;
D O I
10.1109/IROS.2005.1545469
中图分类号
TP18 [人工智能理论];
学科分类号
081104 [模式识别与智能系统]; 0812 [计算机科学与技术]; 0835 [软件工程]; 1405 [智能科学与技术];
摘要
In this paper, FPGA(Field Programmable Gate Array) based hardware architecture for the HIT/DLR Hand has been investigated. With the FPGAs for lower level control and DSP(Digital Signal Processor) for higher level control, the whole hardware is very intelligent. By using the high capacity of FPGAs, the additional hardware such as communication controller and PWM generators, can be implemented in a single chip and the hardware system is more flexible and compact. In each finger there is an FPGA for data collection, brushless DC motors control and communication with palm's FPGA by Point-to-Point Serial Communication (PPSeCo). The kernel of the hardware system is a PCI-based high speed floating-point DSP for data processing, and FPGA for high-speed (up to 25Mbps) real-time serial communication with the palm's FPGA. There needs only 4 cables for the data transmission and the sampling cycle for each sensor is only 200 mu s. This paper presents the basic ideas behind the HIT/DLR Hand's hard- and software architecture adapted to new needs in data processing.
引用
收藏
页码:3233 / 3238
页数:6
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