A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

被引：58

作者：

Saeki, T

Nakaoka, Y

Fujita, M

Tanaka, A

Nagata, K

Sakakibara, K

Matano, T

Hoshino, Y

Miyano, K

Isa, S

Nakazawa, S

Kakehashi, E

Drynan, JM

Komuro, M

Fukase, T

Iwasaki, H

Takenaka, M

Sekine, J

Igeta, M

Nakanishi, N

Itani, T

Yoshida, K

Yoshino, H

Hashimoto, S

Yoshii, T

Ichinose, M

Imura, T

Uziie, M

Kikuchi, S

Koyama, K

Fukuzo, Y

Okuda, T

机构：

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1996年 / 31卷 / 11期

关键词：

D O I：

10.1109/JSSC.1996.542310

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 256-Mb SDRAM (245.7 mm(2)) has been developed using 1) a high cell occupation ratio (60.2%) array design for chip size reduction and a high yield, 2) a prefetched pipeline scheme (PPS) using a first-in first-out (FIFO) buffer with parallel serial converter for 250-MHz clock frequency operation, and 3) a synchronous mirror delay (SMD) circuit for 2,5-ns clock access and low standby current.

引用

页码：1656 / 1668

页数：13