A 0.25-mu m CMOS 0.9 100-MHz DSP core

This paper describes a 0.25-mu m CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less then 1 V has been achieved by developing 0.25-mu m CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages, In addition, short-circuit current and area for diffusion contact are reduced, Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier, Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFET's.