Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs

被引：18

作者：

Lee, Chi-Woo ^{[1
]}

Lederer, Dimitri ^{[1
]}

Afzalian, Aryan ^{[1
]}

Yan, Ran ^{[1
]}

Dehdashti, Nima ^{[1
]}

Xiong, Weize ^{[2
]}

Colinge, Jean-Pierre ^{[1
]}

机构：

[1] Tyndall Natl Inst, Cork, Ireland

[2] Texas Instruments Inc, SiTD, Dallas, TX USA

来源：

SOLID-STATE ELECTRONICS | 2008年 / 52卷 / 11期

基金：

爱尔兰科学基金会;

关键词：

Accumulation-mode; Silicon-on-insulator; Multigate MOSFET;

D O I：

10.1016/j.sse.2008.09.006

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 [电气工程]; 0809 [电子科学与技术];

摘要：

The performances of accumulation-mode and inversion-mode multigate FETs are compared. The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode FETs. (C) 2008 Elsevier Ltd. All rights reserved.

引用

页码：1815 / 1820

页数：6

共 15 条

[1]

Abiko H, 1995, 1995 SYMPOSIUM ON VLSI TECHNOLOGY, P23, DOI 10.1109/VLSIT.1995.520841

[2]

ALLIBERT F, 2001, P IEEE INT SOI C, P149

[3]

High performance and highly reliable novel CMOS devices using accumulation mode multi-gate and fully depleted SOI MOSFETs [J].