COBRA: A 100-MOPS single-chip programmable and expandable FFT

被引：19

作者：

Chen, T ^{[1
]}

Sunada, G ^{[1
]}

Jin, J ^{[1
]}

机构：

[1] Colorado State Univ, Dept Elect Engn, Ft Collins, CO 80523 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 1999年 / 7卷 / 02期

基金：

美国国家科学基金会;

关键词：

bit parallel arithmetic; bit serial arithmetic; column FFT; DFT; FFT; VLSI;

D O I：

10.1109/92.766744

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an optimized column fast Fourier transform (FFT) architecture, which utilizes bit-serial arithmetic and dynamic reconfiguration to achieve a complete overlap between computation and communication. lis a result, for a clock rate of 40 MHz, the system can compute a 24-b precision 1K point complex FFT transform in 9.25 mu s, far surpassing the performance of any existing FFT systems.

引用

页码：174 / 182

页数：9

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