A novel 0.15 mu m CMOS technology using W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusions

被引：17

作者：

Takagi, MT

Miyashita, K

Koyama, H

Nakajima, K

Miyano, K

Akasaka, Y

Hiura, Y

Inaba, S

Azuma, A

Koike, H

Yoshimura, H

Suguro, K

Ishiuchi, H

机构：

来源：

IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996 | 1996年

关键词：

D O I：

10.1109/IEDM.1996.553625

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 0.15 mu m CMOS technology integrating W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusions is presented in this paper. Gate electrode with sheet resistance as low as 1.6 Ohm/sq. and Ti silicided source/drain diffusions of 3.6 Ohm/sq. are realized. As a result, both the gate RC delay and parasitic source/drain resistance are minimized and high circuit performance is achieved.

引用

页码：455 / 458

页数：4