PMOS NBTI-induced circuit mismatch in advanced technologies

被引：9

作者：

Agostinelli, M

Lau, S

Pae, S

Marzolf, P

Muthali, H

Jacobs, S

机构：

[1] Intel Corp, Technol Dev Q&R, Hillsboro, OR 97124 USA

[2] Intel Corp, Intel Commun Grp, Hillsboro, OR 97124 USA

[3] Intel Corp, Portland Technol Dev, Hillsboro, OR 97124 USA

来源：

MICROELECTRONICS RELIABILITY | 2006年 / 46卷 / 01期

关键词：

D O I：

10.1016/j.microrel.2005.05.004

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

PMOS transistor degradation due to negative bias temperature instability (NBTI) has proven to be a significant concern to present CMOS technologies. This is of particular importance for analog applications where the ability to match device characteristics to a high precision is critical. Analog circuits use larger than minimum device dimensions to minimize the effects of process variation, leaving PMOS NBTI as a possible performance limiter. This paper examines the effect of PMOS-NBTI induced mismatch on analog circuits in a 90 nm technology. (c) 2005 Elsevier Ltd. All rights reserved.

引用

页码：63 / 68

页数：6

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