2-v/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell

被引：10

作者：

Hirano, H

Honda, T

Moriwaki, N

Nakakuma, T

Inoue, A

Nakane, G

Chaya, S

Sumi, T

机构：

[1] Kyoto Research Laboratory, Matsushita Electronics Corp., Minami-Ku

[2] Osaka University, Osaka

[3] Kyoto Research Laboratory, Matsushita Electronics Corporation, Kyoto

[4] Okayama University, Okayama

[5] Matsushita Electronics Corporation, Kyoto

[6] Kyusyu University, Fukuoka

[7] Kansai University, Osaka

[8] Matsushita Electronics Corporation, Osaka

[9] Osaka Prefecture University, Osaka

[10] Shinshu University, Nagano

[11] Wasada University, Tokyo

[12] Device Development Department-I, Kyoto Research Laboratory

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1997年 / 32卷 / 05期

关键词：

ferroelectric; memory; nonvolatile; 1T/1C cell;

D O I：

10.1109/4.568826

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Nonvolatile memory embedded in microcontrollers has required a 100 ns access time at 2.0 V for mobile information terminals operating with a rechargeable battery, To achieve this, this paper proposes a new ferroelectric nonvolatile memory (FeRAM) architecture that utilizes a bitline-driven read scheme and a nonrelaxation reference cell for high-speed and low-voltage operations, respectively, Using this architecture, FeRAM with a one transistor and one capacitor per bit (1T/1C) cell can achieve 100 ns access time at 2.0 V.

引用

页码：649 / 654

页数：6