Power dissipation analysis and optimization of deep submicron CMOS digital circuits

被引：101

作者：

Gu, RX ^{[1
]}

Elmasry, MI ^{[1
]}

机构：

[1] UNIV WATERLOO,DEPT ELECT & COMP ENGN,WATERLOO,ON N2L 3G1,CANADA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1996年 / 31卷 / 05期

基金：

加拿大自然科学与工程研究理事会;

关键词：

D O I：

10.1109/4.509853

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the supply voltage, the threshold voltage, and eta, which reflects the drain induced barrier lowing, are also addressed.

引用

页码：707 / 713

页数：7

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