A 0.13-μm SOICMOS technology for low-power digital and RF applications

Battery-operated electronic devices that can communicate wirelessly will become more and more pervasive. This trend will be enabled by technologies that allow low-power digital and RE processing. We present here a 0.13-mum, partially-depleted SOI CMOS technology with optimized power-saving and RF properties (see Table 1 for a list of specifications). Power-saving features include low-Vt, thin-gate-oxide FETs for minimum power dissipation and high performance at low voltage (25 ps inverter delay at 0.7 V Vdd): high-Vt, thick-gate-oxide FETs for low-standby-power SRAM and logic-block power switches; and eight levels of Cu interconnects with low-k ILD Ill. RE features include high peak NFET performance (141 GHz f(T) and 98 GHz f(max) at Vds = 1.2 V) and the following group of high-Q passives: inductor (peak simulated differential Q of 50 at 4 GHz, L = 0.65 nH), MOS varactor, MIMCAP, and resistors.