Low-power design of 8-b embedded CoolRisc microcontroller cores

被引:19
作者
Piquet, C
Masgonty, JM
Arm, C
Durand, S
Schneider, T
Rampogna, F
Scarnera, C
Iseli, C
Bardyn, JP
Pache, R
Dijkstra, E
机构
[1] Ctr. Suisse d'Electron. M.
[2] Centre Electronique Horloger S.A., Neuchâtel
[3] Ctr. Suisse d'Electron. M., Neuchâtel
[4] Swiss Fed. Institute of Technology, Lausanne
关键词
computer architecture; integrated circuit design; micropower; microprocessors; pipeline processing;
D O I
10.1109/4.597297
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Low-power and low-voltage embedded microcontrollers are required more and more for portable applications. Power reduction can be addressed at the software level as well as at the architecture level while searching to reduce the number of executed instructions for a given task. An 8-b RISC-like pipelined microcontroller family is presented achieving one clock per instruction. It is compared to various architectures of existing 8-b microcontrollers. According to an efficiency model taking into account the architecture as well as the number of registers, the presented 8-b microcontroller cores provide four to ten times better performances than existing microcontrollers. On one hand, the operating frequency can be reduced to execute a given task in the same execution time. On the other hand, delivering 10 MIPS performance, more than 2000 MIPS/W can be achieved at 3 V.
引用
收藏
页码:1067 / 1078
页数:12
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