It is well known that systematic within-chip critical dimension (CD) errors can strongly influence product yield and performance, especially in the case of microprocessors. It has been shown that this across chip linewidth variation (ACLV) dominates the CD error budget, and is comprised of multiple systematic and random effects, including substrate reflectivity, reticle CD errors, feature proximity, and lens aberrations. These effects have material, equipment, and process dependencies, with the result being that significant ACLV differences between nominally identical tools/processes can in some cases be observed. We present here a new analysis approach which allows for optimization of exposure I defocus conditions to minimize overall CD errors for a given process. Emphasis is on control of [lmeanl + 3 sigma] of CD errors for a given exposure/defocus condition. Input metrology data is obtained from electrical resistance probing, and data is presented for multiple 248 nn DW processes and tools with CD groundrules ranging from 180 mn to 140 nm.
