Recent advances in flip chip wafer bumping using solder paste technology

被引：15

作者：

Elenius, P ^{[1
]}

Leal, J ^{[1
]}

Ney, J ^{[1
]}

Stepniak, D ^{[1
]}

Yeh, S ^{[1
]}

机构：

[1] Flip Chip Technol, Phoenix, AZ 85034 USA

来源：

49TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1999 PROCEEDINGS | 1999年

关键词：

flip chip; solder bumping; electroless Ni; FOC;

D O I：

10.1109/ECTC.1999.776182

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Flip chip wafer bumping using solder paste technology is currently in high volume production for minimum bump pitches in the range of 150 microns peripheral and 225 microns area array. This paper will also cover the recent advances made in the bumping of wafers with 120 to 150 micron peripheral pitches as well as 200 micron pitch area array pitches. Information on flip chip bump cross sections, height uniformity and shear strength will also be shown. Design rules for utilizing these fine pitch bump structures are shown, including both the bump design rules as well as the IC design rules. A principle advantages of the solder paste bumping technology is the ability to accurately control the solder alloy composition. This capability has been utilized to create a unique lead free solder alloy that is a quaternary alloy. This lead free alloy, which is currently in bump process development, has demonstrated a reliability increase of 50% over that of 63Sn/Pb solder for flip chip applications. Lead free solders provide a potentially feasible path to meet ultra low alpha requirements as well as meeting the coming environmental restrictions on the use of lead. This Pb free alloy has a melting range of 190 to 200C. Flip chips bumped with this alloy were successfully assembled to laminate substrates with a peak reflow temperature of 230C.

引用

页码：260 / 265

页数：6