Power-dissipation driven FPGA place and route under timing constraints

In this paper we address the problem of field programmable gate arrays (FPGA's) place and route for low power dissipation with critical path delay constraints. The presence of a large number of unprogrammed antifuses in the routing architecture adds to the capacitive loading of each net. Hence, a considerable amount of power is dissipated in the routing architecture, due to signal transitions occurring at the output of logic modules. Based on primary input signal distributions, signal activities at the internal nodes of a circuit are estimated. Placement and routing are then carried out, based on the signal activity measure so as to achieve routability with low power dissipation and required timing. Results show that a more than 40% reduction in power dissipation due to routing capacitances can be achieved, compared to a layout based only on area and timing.