Electrical property study of line edge roughness in top surface imaging process by silylation

We have investigated the effect of line edge roughness (LER) of active patterns used for shallow trench isolation to the electrical performance of MOS transistor applicable for 1 giga-bit DRAM. Three different processes for resist patterning were applied for comparative analysis to form the active pattern in MOS transistor; the first method applied a conventional single layer resist (SLR) process, the second TIPS with two step dry development, and the third another TIPS with three step dry development. The third process adopted an additional step to break-through thin silicon dioxide which may contribute to the LER. The LER data of an active pattern before and after nitride substrate etching and their profiles were investigated among these processes. The third method shows the almost same LER and CD uniformity of the active pattern as those of SLR. The electrical properties such as time-dependent dielectric breakdown, 8M full-bar breakdown voltage of gate oxide, junction leakage, and threshold voltage were investigated for MOS transistors which formed by different patterning processes. The third method shows the almost same results with those of first method for these electrical properties. Only, threshold voltage variation of MOS transistor by the second method shows the worse results than those of SLR. Considering the ratio of LER in isolated active pattern with channel width of 0.3 mu m to its average CD value, we think that its ratio should be controlled well below 7% for TIPS to make an useful technology for real device. Based on this studies, we believed that the well-controlled TIPS process using three step dry development is a strong candidate for device production of ArF and EUV lithography, if the advantages of TIPS technology over the SLR process are considered in the respect of lithography.