A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder

被引：368

作者：

Blanksby, AJ ^{[1
]}

Howland, CJ ^{[1
]}

机构：

[1] Agere Syst, High Speed Commun VLSI Syst Res Dept, Holmdel, NJ 07733 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2002年 / 37卷 / 03期

关键词：

CMOS digital integrated circuits; decoding; error correction coding; parallel architectures;

D O I：

10.1109/4.987093

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 1024-b, rate-1/2, soft decision low-density parity-check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of I Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder switching activity resulting in a power dissipation of only 690 mW from a 1.5-V supply.

引用

页码：404 / 412

页数：9

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