A record low 50 nW III/V Tunneling-based SRAM (TSRAM) cell has been demonstrated by combining ultra-low current density resonant-tunneling diodes (RTDs) and heterostructure field effect transistors (HFETs) in one integrated process on an InP substrate. This represents well over two orders of magnitude improvement over previous III/V static memory cells. By increasing the number of vertically integrated RTDs, we have also obtained a 100 nW multi-valued memory cell with three stable states. The cell concept applies to any material system in which low current density negative differential resistance devices are available. An ultralow power one-transistor Si TSRAM cell based on DRAM is also described in anticipation of Si-based RTDs.