Point-to-point connectivity between neuromorphic chips using address events

被引:468
作者
Boahen, KA [1 ]
机构
[1] CALTECH, Carver Meads Lab, Pasadena, CA 91125 USA
基金
美国国家科学基金会;
关键词
asynchronous logic synthesis; interchip communication; spiking neurons; virtual wiring;
D O I
10.1109/82.842110
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper discusses connectivity between neuromorphic chips, which use the timing of fixed-height fixed-width pulses to encode information. Address-events (log(2) (N)-bit packets that uniquely identify one of N neurons) are used to transmit these pulses in real time on a random-access time-multiplexed communication channel. Activity is assumed to consist of neuronal ensembles-spikes clustered in space and in time, This paper quantifies tradeoffs heed in allocating bandwidth, granting access, and queuing, as well as throughput requirements, and concludes that an arbitered channel design is the best choice. The arbitered channel is implemented with a formal design methodology for asynchronous digital VLSI CMOS systems, after introducing the reader to this top-down synthesis technique. Following the evolution of three generations of designs, it is shown. how the overhead of arbitrating, and encoding and decoding, can be reduced in area (from N to root N) by organizing neurons into rows and columns, and reduced in time (from log(2)(N) to 2) by exploiting locality; in the arbiter tree and in the row-column architecture, and clustered activity. Throughput is boosted by pipelining and by reading spikes in parallel. Simple techniques that reduce crosstalk in these mixed analog-digital systems are described.
引用
收藏
页码:416 / 434
页数:19
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