Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFT's for vertical integration applications

被引：40

作者：

Subramanian, V ^{[1
]}

Toita, M

Ibrahim, NR

Souri, SJ

Saraswat, KC

机构：

[1] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA

[2] Asahi Kasei Microsyst Co Ltd, Tokyo 1510053, Japan

来源：

IEEE ELECTRON DEVICE LETTERS | 1999年 / 20卷 / 07期

关键词：

D O I：

10.1109/55.772370

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report on 100-nm channel-length thin-film transistors (TFT's) that are fabricated using germanium-seeded lateral crystallization of amorphous silicon. Germanium-seeding allows the fabrication of devices with control over grain boundary location, Its effectiveness improves with reduced device geometry, allowing "single-grain" device fabrication, In the first application of this technology to deep submicron devices, me report on 100-nm devices having excellent performance compared to conventional TFT's, which have randomly located grains. Devices have on-off ratio >10(6) and subthreshold slope of 107 mV/decade, attesting to the suitability of germanium-seeding for the fabrication of high-performance TFT's, suitable for use in vertically integrated three-dimensional (3-D) circuits.

引用

页码：341 / 343

页数：3

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