Design and implementation of a nanosecond time-stamping readout system-on-chip for photo-detectors

被引：3

作者：

Anvar, Shebli ^{[1
]}

Chateau, Frederic ^{[1
]}

Le Provost, Herve ^{[1
]}

Louis, Frederic ^{[1
]}

Manolopoulos, Konstantinos ^{[2
]}

Moudden, Yassir ^{[1
]}

Vallage, Bertrand ^{[3
]}

Zonca, Eric ^{[1
]}

机构：

[1] CEA Irfu SEDI, Gif Sur Yvette, France

[2] Univ Athens, Dept Phys, GR-10679 Athens, Greece

[3] CEA Irfu SPP, Gif Sur Yvette, France

来源：

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT | 2014年 / 735卷

关键词：

Digital electronic circuits; Data acquisition concepts; Data acquisition circuits; Computing; Large detector-systems performance; Software architectures;

D O I：

10.1016/j.nima.2013.10.019

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

A readout system suitable for a large number of synchronized photo detection units has been designed. Each unit embeds a specifically designed fully integrated communicating system based on Xilinx FPGA SoC technology. It runs the VxWorks real-time OS and a custom data acquisition software designed within the Ice middleware framework, resulting in a highly flexible, controllable and scalable distributed application. Clock distribution and delay calibration over customized fixed latency gigabit Ethernet links enable synchronous time stamping of events with nanosecond precision. The implementation of this readout system on several data-collecting units as well as ifs performances are described. (C) 2013 Published by Elsevier B.V.

引用

页码：587 / 595

页数：9

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