Board-level solder joint reliability comparison of five unique memory package constructions

Sun Microsystems, Inc., a provider of computer hardware, software and services for the technical and commercial marketplace, investigated the board-level solder joint reliability of five unique package constructions of a 54/62 lead memory package. Following a process optimization study, the 0.8/1.0 mm grid chip scale package (CSP) devices were assembled on a complex test board by an advanced board assembly subcontractor, Suzuka Fuji Xerox. In addition to the numerous CSP devices, the test board also included a variety of flip-chip and wirebond EGA packages, and a ceramic column grid array package; only test results of the CSP devices are reported in this paper. Circuit board solder ball land pad (via-in-pad) diameters of 300 mum and 350 mum for the 54/62 lead CSP devices were evaluated. Testing also included a comparison between packages reflowed onto the circuit board using conventional mass reflow furnace, and those using a production rework machine. The circuit board assemblies were temperature cycled between 0 degreesC and 100 degreesC, and electrically monitored for opens. Summary tables and figures comparing the reliability characteristics of the various chip-scale package constructions were generated.