A 125-MHz CMOS mixed-signal equalizer for gigabit ethernet on copper wire

被引：28

作者：

Lee, TC ^{[1
]}

Razavi, B ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90024 USA

来源：

PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2001年

关键词：

D O I：

10.1109/CICC.2001.929740

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A discrete-time mixed-signal linear equalizer designed for the analog front end of Gigabit Ethernet receivers performs cable equalization while relaxing the A/D converter complexity. Based on a coefficient-rotating FIR filter architecture, the circuit incorporates 8 taps that are adapted to the cable characteristics by means of an LMS algorithm. A distributed array of interleaved sampling circuits and a linear low-voltage multiplier topology allow both high speed and low power dissipation. Fabricated in a 0.25-mum digital CMOS technology, the equalizer operates at 125 MHz while dissipating 75 mW from a 2.5-V power supply.

引用

页码：131 / 134

页数：4