Three-dimensional shared memory fabricated using wafer stacking technology

被引：130

作者：

Lee, KW ^{[1
]}

Nakamura, T ^{[1
]}

Ono, T ^{[1
]}

Yamada, Y ^{[1
]}

Mizukusa, T ^{[1
]}

Hashimoto, H ^{[1
]}

Park, KT ^{[1
]}

Kurino, H ^{[1
]}

Koyanagi, M ^{[1
]}

机构：

[1] Tohoku Univ, Dept Machine Intelligence & Syst Engn, Aoba Ku, Sendai, Miyagi 9808579, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904284

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 [电气工程]; 0809 [电子科学与技术];

摘要：

We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.

引用

页码：165 / 168

页数：4