A programmable digital neuro-processor design with dynamically reconfigurable pipeline/parallel architecture

The previous neural network processors are configured either SIMD or Instruction Systolic Array (ISA) Ring architecture with using canonical mapping methodology. Disadvantages of these processors are the lacks of generality, scalability, programmability and veconfigurability. So, we propose a programmable neuro processor which is dynamically reconfigurable it's architecture into either SIM ID or ISA Ring according to the data dependencies of any neural network model. To improve the computing time, the computation of activation function, which needed typically tens of cycle in previous processors, can be done in I cycle by using Piece-Wise Linear (PWL) function approximation. As using simple bus architecture and instruction set, the proposed processor allows the implementation of neural networks larger than the physical PE array and allows user to solve any neural network model. We verify these properties with Error Back- Propagation (EBP) model and estimate the computation time of the proposed processor.