Mesh routing topologies for multi-FPGA systems

被引：20

作者：

Hauck, S ^{[1
]}

Borriello, G

Ebeling, C

机构：

[1] Northwestern Univ, Dept Elect Engn & Comp Sci, Evanston, IL 60208 USA

[2] Univ Washington, Dept Comp Sci & Engn, Seattle, WA 98195 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 1998年 / 6卷 / 03期

基金：

美国国家科学基金会;

关键词：

computer-aided design; gate array; microelectronics; reconfigurable computing; routing;

D O I：

10.1109/92.711311

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

There is currently great interest in using fixed arrays of FPGA's for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGA's. This topology can have a great effect on the area and delay of the resulting system. Crossbar, Hierarchical Crossbar, and Mesh interconnection schemes have all been proposed for use in FPGA-based systems. In this paper, we examine Mesh interconnection schemes, and propose several constructs for more efficient topologies. These reduce interchip delays by more than 60% over the basic four-way Mesh.

引用

页码：400 / 408

页数：9

共 22 条

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