50-nm vertical sidewall transistors with high channel doping concentrations

被引：24

作者：

Schulz, T ^{[1
]}

Rösner, W ^{[1
]}

Risch, L ^{[1
]}

Langmann, U ^{[1
]}

机构：

[1] Infineon Technol AG, Corp Res, D-81730 Munich, Germany

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904259

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Vertical MOSFETs have been proposed in the roadmap of semiconductors as a candidate for sub 100nm CMOS technologies. A process flow using side wall gates and implantations instead of multiple layer depositions reduces process complexity and offers better CMOS compatibility. High doping concentrations in the channel are needed for sub 100nm devices. Especially for vertical transistors the uniform channel doping is more critical than for a planar technology, where optimized profiles can be easier implemented. Therefore, we investigated for the first time vertical MOSFETs with high channel doping concentration up to 1*10(19) cm(-3) and channel lengths down to 50nm. The impact of the high doping levels on threshold voltage and on tunneling currents is discussed. Finally, by using slight process modifications first results on vertical double gate MOSFETs will be presented, which in principle can operate with an undoped channel region.

引用

页码：61 / 64

页数：4