The design of an asynchronous MIPS R3000 microprocessor

被引：109

作者：

Martin, AJ

Lines, A

Manohar, R

Nystrom, M

Penzes, P

Southworth, R

Cummings, U

Lee, TK

机构：

来源：

SEVENTEENTH CONFERENCE ON ADVANCED RESEARCH IN VLSI, PROCEEDINGS | 1997年

关键词：

D O I：

10.1109/ARVLSI.1997.634853

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0.6 mu m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput.

引用

页码：164 / 181

页数：18