FAST-Net optical interconnection prototype demonstration program

This paper reports progress toward the experimental demonstration of a smart pixel based optical interconnection prototype currently being developed under the Free-space Accelerator for Switching Terabit Networks (FAST-Net) project. The prototype system incorporates 2-D arrays of monolithically integrated high-bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs). A key aspect of the FAST-Net concept is that all smart pixels are distributed across a single multi-chip plane. This plane is connected to itself via an optical system that consists of an array of matched lenses (one for each smart pixel chip position) and a mirror. The optical interconnect system implements a global point-to-point shuffle pattern. The interleaved 2-D arrays of VCSELs and PDs in the prototype are arranged on a clustered selfsimilar grid pattern with a closest element pitch of 100 mu m. The circular VCSEL elements have a diameter of 10 mu m and the square PDs have an active region that is 50 mu m wide. These arrays are packaged and mounted on circuit boards along with the CMOS driver, receiver, and FPGA controller chips. Micro-positioning mounts are used to effect alignment that is consistent with current MCM chip placement accuracy. Shuffled optical data links between the multiple ICs have been demonstrated in preliminary evaluation of this system. These results suggest that a multi-Terabit optically interconnected MCM module is feasible.