Influence of silicon surface integrity on device yield

被引：2

作者：

Kimura, Y ^{[1
]}

Naruoka, H ^{[1
]}

Kume, M ^{[1
]}

Katayama, T ^{[1
]}

Yamamoto, H ^{[1
]}

Mashiko, Y ^{[1
]}

机构：

[1] Mitsubishi Elect Corp, ULSI Dev Ctr, Itami, Hyogo 6648641, Japan

来源：

MICROELECTRONIC MANUFACTURING YIELD, RELIABILITY, AND FAILURE ANALYSIS IV | 1998年 / 3510卷

关键词：

GOI; SSI; MWF; wafer surface; pit; Cu; pure water; SC-1; cleaning; Cu decoration;

D O I：

10.1117/12.324374

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

We have investigated the influence of silicon surface integrity (SSI) on LSI device characteristics and yeild. It was found that SSI spoiling during the wafer shaping process causes the reduction of gate oxide integrity (GOI), resulting in poor yield of LSIs. We demonstrated that some analysis techniques, such as long-time SC-1 cleaning, the combination of Cu decoration method and SEM observation and optical shallow defect analyzer (OSDA) are effective for evaluation of SSI. By Cu decoration and SEM observation, many small pits of about 0.03um were observed at GOI failure points. In addition, a model for pit generation was also established in this study. It is thought that Cu ions from contamination takes electrons from activated Si surface in pure water, and oxidized the Si surface partly. The Cu was removed by SC-I final cleaning, and only pits remain on the Si wafer surface. The pits were primary cause of GOI failure and abnormal LPD increase.

引用

页码：169 / 178

页数：10