Floorplanning using a tree representation

被引:57
作者
Guo, PN [1 ]
Takahashi, T
Cheng, CK
Yoshimura, T
机构
[1] Mentor Graph Corp, San Jose, CA 95131 USA
[2] Niigata Univ, Niigata, Japan
[3] Univ Calif San Diego, La Jolla, CA 92093 USA
[4] NEC Corp Ltd, Kawasaki, Kanagawa 213, Japan
基金
美国国家科学基金会;
关键词
building block placement; floorplan; rooted ordered tree;
D O I
10.1109/43.908471
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present an ordered tree (O tree) structure to represent nonslicing floorplans, The O tree uses only n(2 + inverted right perpendicular lg n inverted left perpendicular) bits for a floorplan of n, rectangular blocks. We define an admissible placement as a compacted placement in both a: and y directions. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n!2(2n-2)/n(1.5)). This is very concise compared to a sequence pair representation that has O((n!)(2)) combinations. The approximate ratio of sequence pair and O-tree combinations is O(n(2)(n/4e)(n)), The complexity of O tree is even smaller than a binary tree structure for slicing floorplan that has O(n!2(5n-3)/n(1.5)) combinations, Given an O tree, it takes only linear time to construct the placement and its constraint graph, We have developed a deterministic floorplanning algorithm utilizing the structure of O tree. Empirical results on MCNC (www.mcnc.org) benchmarks show promising performance with average 16% improvement in wire length and 1% less dead space over previous central processing unit (CPU) intensive cluster refinement method.
引用
收藏
页码:281 / 289
页数:9
相关论文
共 15 条
[1]  
DIESTEL R, 1997, GRAPH THEORY, P81
[2]   SHORT ENCODINGS OF PLANAR GRAPHS AND MAPS [J].
KEELER, K ;
WESTBROOK, J .
DISCRETE APPLIED MATHEMATICS, 1995, 58 (03) :239-252
[3]  
KNUTH DE, 1973, ART COMPUTER PROGRAM, V1, P385
[4]  
LENGAUER T, 1990, COMBINATORIAL ALGORI, P328
[5]  
Murata H., 1995, P ICCAD, P472
[6]  
ONODERA H, 1991, P 28 ACM IEEE DES AU, P433
[7]  
OTTEN RHJ, 1982, P 19 ACM IEEE DES AU, P261
[8]   AREA MINIMIZATION FOR FLOORPLANS [J].
PAN, PC ;
LIU, CL .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1995, 14 (01) :123-132
[9]  
PREAS B, 1988, PHYSICAL DESIGN AUTO, P129
[10]  
PREAS BT, 1979, P ACM IEEE DES AUT C, P474