The Level-0 muon trigger for the LHCb experiment

被引:6
作者
Aslanides, E. [1 ]
Cachemiche, J.-P. [1 ]
Cogan, J. [1 ]
Dinkespiler, B. [1 ]
Favard, S. [1 ]
Duval, P.-Y. [1 ]
Le Gac, R. [1 ]
Leroy, O. [1 ]
Liotard, P.-L. [1 ]
Marin, F. [1 ]
Menouni, M. [1 ]
Roche, A. [1 ]
Tsaregorodtsev, A. [1 ]
机构
[1] Univ Aix Marseille 1, CNRS, Ctr Phys Particles Marseille, IN2P3, Marseille, France
关键词
first level trigger; high speed serial link; high density FPGA; muon detector; LHCb;
D O I
10.1016/j.nima.2007.06.022
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
A very compact architecture has been developed for the first level muon trigger of the LHCb experiment that processes 40 x 10(6) proton-proton collisions per second. For each collision, it receives 3.2 kBytes of data and it finds straight tracks within a 1.2 mu s latency. The trigger implementation is massively parallel, pipelined and fully synchronous with the LHC clock. It relies on 248 high density Field Programable Gate Arrays and on the massive use of multigigabit serial link transceivers embedded inside FPGAs. (c) 2007 Elsevier B.V. All rights reserved.
引用
收藏
页码:989 / 1004
页数:16
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