Extended data retention process technology for highly reliable flash EEPROMs of 106 to 107 W/E cycles

Using 16Mbit flash memories, we clarified the relation between data retentivity and Si surface micro-defects just before the tunnel oxidation process. After 10(5) to 10(6) write/erase cycles, a small number of singular cells appear to have an anomalously large charge loss rate, when the Si surface defect density due to process damage exceeds 1.2x10(20)/cm(3). This anomalous charge loss phenomenon strongly depends on the electric field in the tunnel oxide, which is caused by the stored charge in the floating gate. Thus, an accelerated data retention test can be performed by means of the electric field in the tunnel oxide, by controlling the programmed Vt to be more than 2.4V just before the retention test (here, neutral Vt is adjusted to OV). By using an accelerated test, it is clarified that controlling the number of surface micro-defects is important to obtain the extended data retention characteristics. By reducing the surface micro-defects to less than 1.2x10(20)/cm(3), the data retention reliability alter 10(6) to 10(7) write/erase cycles can be guaranteed for conventional 2-level Flash memories, where programmed Vt is less than 2.4V.