A 3.3V analog adaptive line-equalizer for Fast Ethernet data communication

被引：38

作者：

Babanezhad, JN ^{[1
]}

机构：

[1] Plato Labs, San Jose, CA USA

来源：

IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/CICC.1998.694995

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An adaptive line-equalizer has been developed for 100Mb/sec Fast Ethernet data communication. For a 100m CAT3 UTP cable the output jitter is 2nsec while for that of a 125m CATS UTP cable it is 2.8nsec. The device is fabricated in 0.4 mu digital CMOS process where it consumes 65mW from a 3.3V power supply.

引用

页码：343 / 346

页数：4