Ultra fine-pitch wafer level packaging with reworkable composite nano-interconnects

The decrease in feature sizes of micro-electronic devices has underlined the need for higher number of I/O's in order to increase its functionality. This has spurred a great interest in developing electronic packages with fine and ultra fine pitches (20-100 microns). Most of the compliant interconnects that . are currently being developed have inductance and resistance higher than desirable. This paper presents a novel low-temperature fabrication process that combines polymer structures with electroless copper plating to create low stress MEMS structures for extremely fine pitch wafer level packages. Finite Element Analysis of these structures shows tremendous reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Low CTE polyintide structures with ultra-low stress, high toughness and strength were fabricated using plasma etching. This dry etching process was tuned to yield a wall angle above 80 degrees. The etching process also leads to roughened sidewalls for selective electroless copper plating on the sidewalls of polymer structures. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. This work also describes a material solution synthesis route to develop reworkable nano-dimensional interfaces for IC-package bonding. Reworkability is addressed by a thin (200 nm) interface of lead-free high-strength solders using selective electroless plating. Lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents at 45 degrees C. The lead-free solder composition was controlled by altering the plating bath formulation and was characterized using SEM, XRD and XPS. Solder film formed from the above approach was demonstrated to bond the metal-coated polymer interconnects with the copper pads on the substrate.