Ultra-short 25-nm-gate lattice-matched InAlAs/InGaAs HEMTs within the range of 400 GHz cutoff frequency

被引：71

作者：

Yamashita, Y ^{[1
]}

Endoh, A

Shinohara, K

Higashiwaki, M

Hikosaka, K

Mimura, T

Hiyamizu, S

Matsui, T

机构：

[1] Fujitsu Ltd, Kanagawa 2430197, Japan

[2] Commun Res Labs, Tokyo 1840015, Japan

[3] Osaka Univ, Grad Sch Engn, Osaka 5608531, Japan

来源：

IEEE ELECTRON DEVICE LETTERS | 2001年 / 22卷 / 08期

关键词：

cutoff frequency; gate length; HEMT; high electron mobility transistor; InAlAs/InGaAs; InP; low-temperature process; two-step-recessed gate;

D O I：

10.1109/55.936345

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have succeeded in fabricating ultra-short 25-nm-gate InAlAs/InGaAs high electron mobility transistors (HEMTs) lattice-matched to InP substrates, The two-step-recessed gate technology and low temperature processing at below 300 degreesC allowed the fabrication of such ultra-short gates. DC measurements showed that the 25-nm-gate HEMT had good pinchoff behavior. We obtained a cutoff frequency f(T) of 396 GHz, within the range of 400 GHz f(T), for the 25-nm-gate HEMT. This f(T) is the highest value yet reported for any type of transistor, and the gate length of 25 mm is the shortest value ever reported for any compound semiconductor transistor that exhibits device operation.

引用

页码：367 / 369

页数：3

共 9 条

[1] ELIMINATION OF MESA-SIDEWALL GATE LEAKAGE IN INA1AS/INGAAS HETEROSTRUCTURES BY SELECTIVE SIDEWALL RECESSING [J].

BAHL, SR ;

DELALAMO, JA .

IEEE ELECTRON DEVICE LETTERS, 1992, 13 (04) :195-197

[2] High fT 50-nm-gate lattice-matched InAlAs/InGaAs HEMTs [J].

Endoh, A ;

Yamashita, Y ;

Higashiwaki, M ;

Hikosaka, K ;

Mimura, T ;

Hiyamizu, S ;

Matsui, T .

2000 INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS, CONFERENCE PROCEEDINGS, 2000, :87-90

[3] 0.05-MU-M-GATE INALAS/INGAAS HIGH-ELECTRON-MOBILITY TRANSISTOR AND REDUCTION OF ITS SHORT-CHANNEL EFFECTS [J].

ENOKI, T ;

TOMIZAWA, M ;

UMEDA, Y ;

ISHII, Y .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 1994, 33 (1B) :798-803

[4] 50-NM SELF-ALIGNED-GATE PSEUDOMORPHIC ALINAS GAINAS HIGH ELECTRON-MOBILITY TRANSISTORS [J].

NGUYEN, LD ;

BROWN, AS ;

THOMPSON, MA ;

JELLOIAN, LM .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (09) :2007-2014

[5] 30-nm-gate InP-based lattice-matched high electron mobility transistors with 350 GHz cutoff frequency [J].

Suemitsu, T ;

Ishii, T ;

Yokoyama, H ;

Enoki, T ;

Ishii, Y ;

Tamamura, T .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS, 1999, 38 (2B) :L154-L156

[6] Improved recessed-gate structure for sub-0.1-μm-gate InP-based high electron mobility transistors [J].

Suemitsu, T ;

Enoki, T ;

Yokoyama, H ;

Ishii, Y .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 1998, 37 (3B) :1365-1372

[7]

SUEMITSU T, 2000, 2000 TOP WORKSH HET, P2

[8] Novel high-yield trilayer resist process for 0.1 mu m T-gate fabrication [J].

Wakita, AS ;

Su, CY ;

Rohdin, H ;

Liu, HY ;

Lee, A ;

Seeger, J ;

Robbins, VM .

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1995, 13 (06) :2725-2728

[9] High fT 50-nm-gate InAlAs/InGaAs high electron mobility transistors lattice-matched to InP substrates [J].