Tailoring of isolation structures with tap-surface imaging process by silylation

It is well known that TIPS(Top-surface Imaging Process by Silylation) process has a feasibility to overcome lots of problems induced from single-layer resist process. Nevertheless, chip makers have been reluctant to apply this process to giga technology with two major issues; process issues such as Line Edge Roughness (LER), residues, Critical Dimension (CD) uniformity, and rework scheme and infrastructure issues of system reliability and reproducibility. First of all, the process issues should be investigated to realize the giga device manufacturing. In this paper, we will describe the patterning results of 180nm isolation structure of 1G bit DRAM on process issues. LER is a critical problem that arises from edge breakdown of thin SiOx mask generated from silylated resist during dry development. We have tried to get roughness smaller by means of the prevention of edge-breakdown of SiOx mask. Residues on the unexposed area due to unwanted silylation after dry development disappeared by using an optimized C2F6/O-2 break-through step. In this experimental, the optimum process conditions for removing of LER and residues were determined by controlling the condition of dry development. The results are compared to those obtained using two-step and three-step dry development. We achieved excellent 3sigma values of 17nm and 20nm for CD uniformity within a chip and a wafer, respectively. We have also developed rework procedures to remove the resist pattern formed after dry development by using BOE and clean-D (mixture of H2SO4 and H2O2) solutions. From these studies, it was confirmed that TIPS process using a cluster-tool silylation system incorporating a LRC TCPTM 9400SE dry development module was verified as a production-worthy process for 180nm isolation pattern formation.