An embedded FeRAM macro cell for a smart card microcontroller

被引：10

作者：

Miwa, T ^{[1
]}

Yamada, J ^{[1
]}

Okamoto, Y ^{[1
]}

Koike, H ^{[1
]}

Toyoshima, H ^{[1
]}

Hada, H ^{[1
]}

Hayashi, Y ^{[1
]}

Okizaki, H ^{[1
]}

Miyasaka, Y ^{[1
]}

Kunio, T ^{[1
]}

Miyamoto, H ^{[1
]}

Gomi, H ^{[1
]}

Kitajima, H ^{[1
]}

机构：

[1] NEC Corp, Silicon Syst Res Labs, Sagamihara, Kanagawa 2291198, Japan

来源：

IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/CICC.1998.695014

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the circuit technologies and the experimental results for an embedded FeRAM macro cell for a smart. card microcontroller. This macro cell employs a 256 byte 2T/2C FeRAM cell array for rewritable nonvolatile memory storage. The macro cell performs read/write operations that are fully synchronous with the microprocessor core, and its write operations are over 1000 times faster than the program operations of a conventional EEPROM macro cell. The macro cell is provided with developed offset sense amplifiers for screening out ally weak cells in write endurance. With a small memory cell, as well as a small charge pumping circuit and write circuits, the FeRAM macro cell occupies only half the area of an EEPROM macro. A prototype microcontroller provided with the FeRAM macro cell is fabricated in a standard double metal layer CMOS process with added ferroelectric capacitor process steps.

引用

页码：439 / 442

页数：4